Media Contact : For Immediate Release

In the first-ever demonstration of FinFET technology suitable for 10-nm CMOS manufacturing – pushing device scaling two nodes beyond the current leading-edge volume production technology – Samsung and others will jointly showcase a platform technology for low-power and high-performance applications. It offers the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported on both bulk and SOI substrates. A 0.053 µm 2 SRAM bit-cell is reported with a low corresponding static noise margin of 140 mV at 0.75 V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. A multi-workfunction gate stack provides Vt tunability without the variability degradation channel dopants induce.